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Moving Learning Machine Towards Fast Real-Time Applications: A High-Speed FPGA-based Implementation of the OS-ELM Training Algorithm

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Moving Learning Machine Towards Fast Real-Time Applications: A High-Speed FPGA-based Implementation of the OS-ELM Training Algorithm

dc.contributor.author	Francés Villora, José Vicente
dc.contributor.author	Rosado Muñoz, Alfredo
dc.contributor.author	Bataller Mompean, Manuel
dc.contributor.author	Barrios Avilés, Juan
dc.contributor.author	Guerrero Martínez, Juan Francisco
dc.date.accessioned	2018-12-17T15:08:42Z
dc.date.available	2018-12-17T15:08:42Z
dc.date.issued	2018
dc.identifier.citation	Francés Villora, José Vicente Rosado Muñoz, Alfredo Bataller Mompean, Manuel Barrios Avilés, Juan Guerrero Martínez, Juan Francisco 2018 Moving Learning Machine Towards Fast Real-Time Applications: A High-Speed FPGA-based Implementation of the OS-ELM Training Algorithm Electronics 7 11 308
dc.identifier.uri	http://hdl.handle.net/10550/68284
dc.description.abstract	Currently, there are some emerging online learning applications handling data streams in real-time. The On-line Sequential Extreme Learning Machine (OS-ELM) has been successfully used in real-time condition prediction applications because of its good generalization performance at an extreme learning speed, but the number of trainings by a second (training frequency) achieved in these continuous learning applications has to be further reduced. This paper proposes a performance-optimized implementation of the OS-ELM training algorithm when it is applied to real-time applications. In this case, the natural way of feeding the training of the neural network is one-by-one, i.e., training the neural network for each new incoming training input vector. Applying this restriction, the computational needs are drastically reduced. An FPGA-based implementation of the tailored OS-ELMalgorithm is used to analyze, in a parameterized way, the level of optimization achieved. We observed that the tailored algorithm drastically reduces the number of clock cycles consumed for the training execution up to approximately the 1%. This performance enables high-speed sequential training ratios, such as 14 KHz of sequential training frequency for a 40 hidden neurons SLFN, or 180 Hz of sequential training frequency for a 500 hidden neurons SLFN. In practice, the proposed implementation computes the training almost 100 times faster, or more, than other applications in the bibliography. Besides, clock cycles follows a quadratic complexity O(N 2), with N the number of hidden neurons, and are poorly influenced by the number of input neurons. However, it shows a pronounced sensitivity to data type precision even facing small-size problems, which force to use double floating-point precision data types to avoid finite precision arithmetic effects. In addition, it has been found that distributed memory is the limiting resource and, thus, it can be stated that current FPGA devices can support OS-ELM-based on-chip learning of up to 500 hidden neurons. Concluding, the proposed hardware implementation of the OS-ELM offers great possibilities for on-chip learning in portable systems and real-time applications where frequent and fast training is required.
dc.language.iso	eng
dc.relation.ispartof	Electronics, 2018, vol. 7, num. 11, p. 308
dc.subject	Enginyeria elèctrica
dc.subject	Enginyeria d'ordinadors
dc.title	Moving Learning Machine Towards Fast Real-Time Applications: A High-Speed FPGA-based Implementation of the OS-ELM Training Algorithm
dc.type	journal article	es_ES
dc.date.updated	2018-12-17T15:08:42Z
dc.identifier.doi	10.3390/electronics7110308
dc.identifier.idgrec	128936
dc.rights.accessRights	open access	es_ES